Memory arrays may be based on various arrangements and/or types of bit-cells. Crosspoint arrays, serial arrangements of one-transistor one-memristor (1T1R) bit-cells, serial array arrangements of parallel 1T1R bit-cells, and other arrangements may suffer from various issues (poor selectivity, power losses, unselected cells not being properly bypassed, etc.). Other arrangements may suffer from an increased need for space, reducing potential circuit densities.